(1) Field of the Invention
The present invention relates to a programmable semiconductor memory device, and more particularly, to a programmable semiconductor memory device such as a programmable read memory (PROM), a field programmable logic array, (FPLA), and the like, in which a write-only word line driver and a read word line driver are provided separately to improve the accessing speed to a word line during a read operation.
(2) Description of the Related Art
In general, a programmable semiconductor memory device comprises programmable memory cells arranged on respective intersecting portions between a plurality of word lines and a plurality of bit lines. Writing data into or reading data from a selected memory cell is carried out by driving a selected bit line and a selected word line. The selection of the word line is effected by a word line address decoder. The driving of the word line is effected by a word line driver. That is, writing data into or reading data from the selected programmable memory cell is carried out by absorbing a current from the selected bit line, through the selected memory cell and through the selected word line, into the word line driver.
Because the accessing speed for the selection and driving of a word line is increased with the decrease of the emitter area of each output transistor in the word line driver, the emitter area of the output transistor should be large enough to enable it to withstand the electric current absorbed by the word line driver.
Conventionally, a single word line driver is commonly used both for writing and for reading. The current absorbed during writing, however, is much larger than the current absorbed during reading, as later described in more detail with reference to the drawings. Therefore, the emitter areas of the output transistors in the word line driver are designed to be able to withstand the write-in currents. However, because of the resulting large emitter area, the output transistor has a large parasitic capacitance, which raises a problem of an undesirable reduction of the accessing speed to a word line during a usual read operation.